1. Field of the Invention
The present invention relates generally to a direct conversion transceiver, and more particularly, to a direct conversion transceiver for reducing DC offset.
2. Description of the Related Art
Although the size, power consumption, and costs of a current portable radio terminal are remarkably reduced compared to the early stage of development thereof, there is still the need to further reduce the size, power consumption, and costs of the current portable radio terminal and to manufacture a portable radio terminal having a better quality.
A direct conversion architecture is a structure from which an image rejection filter is removed. The number of components used in the direct conversion architecture is reduced such that the size and power consumption of the portable radio terminal are reduced.
However, in order to apply such a direct conversion architecture to a portable radio terminal, a problem occurs during mixing that creates a DC offset. Further, it is difficult to distinguish such a DC offset from an actual signal, and the DC offset causes an amplifier provided at a next stage of a mixer to saturate.
In order to solve the above-described DC offset problem, several methods have been suggested, and a new method is currently under development. FIGS. 1 and 2 each illustrate an example of a method for reducing a DC offset in a conventional direct conversion transceiver.
Referring to FIG. 1, signals received through an antenna 10 are amplified by a first amplifier 12 and are mixed with a reference signal generated in a local oscillator 34 by first and second mixers 14 and 16. In this procedure, carrier signals are eliminated from the signals. When the signals, which are output from the first and second mixers 14 and 16 and from which the carrier signals have been eliminated, go through first and second low pass filters (LPFs) 18 and 20, high frequency components are eliminated. Signals output from the first and second LPFs 18 and 20 are amplified by second and third amplifiers 26 and 30. Reference numeral 36 denotes a phase shifter for shifting the phase of the reference signal generated in the local oscillator 34 by 90 degrees.
Referring to FIG. 3, due to substrate coupling and bond wire coupling, oscillator signal leakage 50 occurs when a reference signal cos WLOt is input into the first mixer 14 from a local oscillator (not shown). In addition, as illustrated in FIG. 4, due to substrate coupling and bond wire coupling, large interference leakage 52 occurs when the first amplifier 12 amplifies the signals received through the antenna 10. Leakage signals are self-mixed with a reference signal generated from the local oscillator, for example, as shown in Equation 1, and as a result, a DC offset occurs.
                              cos          ⁢                                          ⁢                      w            LO                    ⁢          t          ×          cos          ⁢                                          ⁢                      w            LO                    ⁢          t                =                              1            +                          cos              ⁢                                                          ⁢              2              ⁢                              w                LO                            ⁢              t                                2                                    (        1        )            
The DC offset corresponding to ½ in Equation 1 causes the second amplifier 26, which is provided at a next stage of the first mixer 14, to saturate. In addition, the DC offset becomes irregular when signals are irradiated by the antenna 10, are reflected, and are received again. Additionally, it is difficult to distinguish the DC offset from the signals actually received.
In order to eliminate such a DC offset, the prior art illustrated in FIG. 1 includes a first capacitor 22 between the first LPF 18 and the second amplifier 26 and a second capacitor between the second LPF 20 and the third amplifier 30. However, in the prior art, the volume of the first and second capacitors 22 and 24 is large, and additional grounds 28 and 32 for charge and discharge are needed. As a result, the size of the circuit is increased, and it is difficult to produce it as a single chip IC. In addition, an application thereof is defined by time division multiple access (TDMA).
FIG. 2 illustrates a conventional direct conversion receiver as disclosed in Japanese Patent Publication Laid-open No. He 3-220823. More specifically, FIG. 2 illustrates a method of eliminating the above-described DC offset by a negative feedback loop. The negative feedback loop comprises a first analog to digital converter (A/D) converter 40 placed between a second amplifier 26 and a data processing circuit 44, a second A/D converter 42 placed between a third amplifier 30 and the data processing circuit 44, a first digital to analog (D/A) converter 46 placed between a first mixer 14 and the data processing circuit 44, for converting a predetermined digital signal output from the data processing circuit 44 into an analog signal and feeding back the analog signal to the first mixer 14, and a second D/A converter 48 placed between a second mixer 16 and the data processing circuit 44, for converting the predetermined digital signal into an analog signal and feeding back the analog signal to the second mixer 16. However, by use of a closed loop, a loop convergence time is restricted. As a result, like in a portable radio terminal, it is difficult to use the direct conversion receiver in a device having a short time slot.
Additionally, U.S. Pat. No. 6,175,728 discloses a direct conversion receiver with a delta-sigma modulator and a switch capable of canceling a DC offset voltage in real-time. However, because a switching time is required, an application of the direct conversion receiver is defined by time division multiple access (TDMA), and the size of a circuit is increased.